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micro pmu with 800 ma buck, 300 ma ldo, supervisory, watchdog, and manual rese t adp5043 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features input voltage range: 2.3 v to 5.5 v one 800 ma buck regulator one 300 ma ldo 20-lead, 4 mm 4 mm lfcsp package initial regulator accuracy: 1% overcurrent and thermal protection soft start undervoltage lockout open-drain processor reset with threshold monitoring 1.5% threshold accuracy over the full temperate range guaranteed reset output valid to v cc = 1 v dual watchdog for secure systems watchdog 1 controls reset watchdog 2 controls reset and regulators power cycle buck regulator key specifications current-mode topology for excellent transient response 3 mhz operating frequency uses tiny multilayer inductors and capacitors mode pin selects forced pwm or auto pfm/psm modes 100% duty cycle low dropout mode ldo key specifications low v in from 1.7 v to 5.5 v stable with1 f ceramic output capacitors high psrr, 60 db up to 1 khz/10 khz low output noise low dropout voltage: 150 mv at 300 ma load ?40c to +125c junction temperature range general description the adp5043 combines one high performance buck regulator and one low dropout regulator (ldo) in a small 20-lead lfcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space. the mode pin selects the bucks mode of operation. when set to logic high, the buck regulator operates in forced pwm mode. when the mode pin is set to logic low, the buck regulator operates in pwm mode when the load is around the nominal value. when the load current falls below a predefined threshold, the regulator operates in power save mode (psm) improving the light-load efficiency. the low quiescent current, low dropout voltage, and wide input voltage range of the adp5043 ldo extend the battery life of portable devices. the ldo maintains a power supply rejection of greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. each regulator is activated by a high level on the respective enable pin. the adp5043 is available with factory programmable default output voltages and can be set to a wide range of options. the adp5043 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. the adp5043 also provides power-on reset signals. an on-chip dual watchdog timer can reset the microprocessor or power cycle the system (watchdog 2) if it fails to strobe within a preset timeout period. high level block diagram vin wd1 mode selection fpwm psm/pwm mode sw vout1 pgnd c6 10f l1 1h en_bk buck en_ldo ldo vin1 en1 vin2 en2 c2 1f vout2 gnd gnd c5 4.7f on off on off nc vin1 = 2.3v to 5.5v avin r filt 30? vin2 = 1.7v to 5.5v mr c1 1f microprocessor supervisor wstat wmod wdi1 wdi2 nrsto nc agnd avin avin adp5043 v out1 @ 800ma v out2 @ 300ma 09682-001 figure 1.
adp5043 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 general description ......................................................................... 1 high level block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 general specifications ................................................................. 3 supervisory specifications .......................................................... 3 buck specifications....................................................................... 5 ldo specifications ...................................................................... 5 input and output capacitor, recommended specifications.. 6 absolute maximum ratings............................................................ 7 thermal data ................................................................................ 7 thermal resistance ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 16 power management unit........................................................... 16 buck section................................................................................ 17 ldo section ............................................................................... 18 supervisory section ................................................................... 18 applications information .............................................................. 21 buck external component selection....................................... 21 ldo capacitor selection .......................................................... 22 supervisory section ................................................................... 23 pcb layout guidelines.............................................................. 24 power dissipation/thermal considerations ............................. 25 evaluation board schematics and artwork............................ 27 suggested layout ........................................................................ 27 bill of materials........................................................................... 28 application diagram ................................................................. 28 factory programmable options ................................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 4/11revision 0: initial version
adp5043 rev. 0 | page 3 of 32 specifications general specifications avin, vin1 = (v out1 + 0.5 v) or 2.3 v, whichever is greater, avin, vin1 vin2, t a = 25c, unless otherwise noted. regulators are enabled. table 1. parameter symbol test conditions/comments min typ max unit avin undervoltage lockout uvlo avin t j = ?40c to +125c input voltage rising uvlo avinrise option a 2.25 v option b 3.9 v input voltage falling uvlo avinfall option a 1.95 v option b 3.1 v shutdown current i gnd-sd enx = gnd 0.1 a enx = gnd, t j = ?40c to +125c 2 a thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd-hys 20 c enx, wdix, mode, wmod, mr inputs input logic high v ih 2.5 v avin 5.5 v 1.2 v input logic low v il 2.5 v avin 5.5 v 0.4 v input leakage current (wmod excluded) v i-leakage enx = avin or gnd 0.05 a enx = avin or gnd, t j = ?40c to +125c 1 a wmod input leakage current v i-lkg-wmod vwmod = 3.6 v, t j = ?40c to +125c 50 a open-drain outputs nrsto, wstat output voltage v ol avin = 2.3 v to 5.5 v, i nrsto/wstat = 3 ma 30 mv open-drain reset output leakage current 1 a supervisory specifications avin, vin1 = full operating range, t j = ?40c to +125c, unless otherwise noted. table 2. parameter min typ max unit test conditions/comments supply supply current (supervisory circuit only) 45 55 a avin = 5.5 v, en1 = en2 = vin1 43 52 a avin = 3.6 v, en1 = en2 = vin1 reset threshold accuracy v th ? 0.8% v th v th + 0.8% v t a = 25c, sensed on voutx v th ? 1.5% v th v th + 1.5% v t j = ?40c to +125c, sensed on v outx reset threshold to output delay glitch immunity (t uod ) 50 125 400 s v th = v out ? 50 mv reset timeout period watchdog1 (t rp1 ) option a 24 30 36 ms option b 160 200 240 ms reset timeout period watchdog2 (t rp2 ) 3.5 5 7 ms v cc to reset delay (t rd ) 150 s vin1 falling at 1 mv/s regulators sequencing delay (t d1 , t d2 ) 2 ms watchdog inputs watchdog 1 timeout period (t wd1 ) option a 81.6 102 122.4 ms option b 1.28 1.6 1.92 sec
adp5043 rev. 0 | page 4 of 32 parameter min typ max unit test conditions/comments watchdog 2 timeout period (t wd2 ) option a 6 7.5 9 sec option b watchdog 2 disabled option c 3.2 4 4.8 min option d 6.4 8 9.6 min option e 11.2 16 19.2 min option f 25.6 32 38.4 min option g 51.2 64 76.8 min option h 102.4 128 153.8 min watchdog 2 power off period (t poff ) option a 210 ms option b 400 ms wdi1 pulse width 80 ns v il = 0.4 v, v ih = 1.2 v wdi2 pulse width 8 s v il = 0.4 v, v ih = 1.2 v watchdog status timeout period (t wdclear ) 11.2 sec wdi1 input current (source) 8 15 20 a v wdi1 = v cc , time average wdi1 input current (sink) ?30 ?25 ?14 a v wdi1 = 0, time average wdi2 internal pull-down 45 k manual reset input mr input pulse width 1 s mr glitch rejection 220 ns mr pull-up resistance 25 52 80 k mr to reset delay 280 ns v cc = 5 v
adp5043 rev. 0 | page 5 of 32 buck specifications avin, vin1 = 3.6 v, v out1 = 1.8 v, t j = ?40c to +125c for minimum/maximum specifications, l = 1 h, c out = 10 f, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3. parameter test conditions/comments min typ max unit input characteristics input voltage range (vin1) 2.3 5.5 v output characteristics output voltage accuracy pwm mode, i load = 100 ma ?1 +1 % psm mode ?2 +2 % vin1 = 2.3 v to 5.5 v, pwm mode, i load = 1 ma to 800 ma ?3 +3 % pwm to power save mode current threshold 100 ma input current characteristics dc operating current i load = 0 ma, device not switching 21 35 a shutdown current enx = 0 v, t a = t j = ?40c to +125c 0.2 1.0 a sw characteristics sw on resistance pfet 180 240 m pfet, avin = vin1 = 5 v 140 190 m nfet 170 235 m nfet, avin = vin1 = 5 v 150 210 m current limit pfet switch peak current limit 1100 1360 1600 ma active pull-down en1 = 0 v 75 oscillator frequency 2.5 3.0 3.5 mhz start-up time 250 s 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). ldo specifications avin = 3.6 v, vin2 = (vout2 + 0.2 v) or 2.3 v, whichever is greater; avin, vin1 vin2; i out = 10 ma; c in = c out = 1 f; t a = 25c, unless otherwise noted. table 4. parameter symbol test conditions/comments min typ max unit input voltage range v in2 t j = ?40c to +125c 1.7 5.5 v operating supply current (per ldo) i gnd i out = 0 a, vout = 3.3 v 15 a i out = 0 a, vout = 3.3 v, t j = ?40c to +125c 50 a i out = 10 ma 67 a i out = 10 ma, t j = ?40c to +125c 105 a i out = 200 ma 100 a i out = 200 ma, t j = ?40c to +125c 245 a fixed output voltage accuracy v out2 i out = 10 ma ?1 +1 % 100 a < i out < 300 ma ?2 +2 % vin2 = (vout2 + 0.5 v) to 5.5 v 100 a < i out < 300 ma ?3 +3 % vin2 = (vout2 + 0.5 v) to 5.5 v t j = ?40c to +125c
adp5043 rev. 0 | page 6 of 32 parameter symbol test conditions/comments min typ max unit regulation line regulation ?v out2 /?v in2 vin2= (vout2 + 0.5 v) to 5.5 v ?0.03 +0.03 %/ v i out2 = 1 ma t j = ?40c to +125c load regulation 1 ?v out2 /?i out2 i out2 = 1 ma to 200 ma 0.002 %/ma i out2 = 1 ma to 200 ma 0.0075 %/ma t j = ?40c to +125c dropout voltage 2 v dropout vout2 = 3.3 v i out2 = 10 ma 4 mv i out2 = 10 ma, t j = ?40c to +125c 5 mv i out2 = 200 ma 60 mv i out2 = 200 ma, t j = ?40c to +125c 100 mv active pull-down r pdldo en2 = 0 v 600 start-up time t start-up vout2 = 3.3 v 85 s current-limit threshold 3 i limit t j = ?40c to +125c 335 470 ma output noise out ldonoise 10 hz to 100 khz, vin2 = 5 v, vout2 = 3.3 v 123 v rms 10 hz to 100 khz, vin2 = 5 v, vout2 = 2.8 v 110 v rms 10 hz to 100 khz, vin2 = 5 v, vout2 = 1.5 v 59 v rms power supply rejection ratio psrr 1 khz, vin2 = 3.3 v, vout2 = 2.8 v, i out = 100 ma 66 db 100 khz, vin2 = 3.3 v, vout2 = 2.8 v, i out = 100 ma 57 db 1 mhz, vin2 = 3.3 v, vout2 = 2.8 v, i out = 100 ma 60 db 1 based on an en d-point calculation using 1 ma and 100 ma loads. 2 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.3 v. 3 current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output capacitor, recommended specifications table 5. parameter symbol test conditions/comments min typ max unit output capacitance (buck) 1 c min1 t j = ?40c to +125c 7 40 f minimum input and output capacitance 2 (ldo) c min2 t j = ?40c to +125c 0.70 f capacitor esr r esr t j = ?40c to +125c 0.001 1 1 the minimum output capacitance should be greater than 4.7 f over the full range of operating conditions. the full range of op erating conditions in the application must be considered during device selection to ensu re that the minimum capacita nce specification is met. 2 the minimum input and output capacitance should be greater than 0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during devi ce selection to ensure that the minimum capa citance specification is met. x7r and x5r type capacitors are recommended, y5v and z5u capacitors are not recommended for use with ldos or the buck.
adp5043 rev. 0 | page 7 of 32 absolute maximum ratings table 6. parameter rating avin, vinx, voutx, enx, mode, mr , wdix, wmod, wstat, nrsto to gnd ?0.3 v to +6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 esd human body model 3000 v esd charged device model 1500 v esd machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp5043 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temper- ature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package. maxi- mum junction temperature is calculated from the ambient temperature and power dissipation using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified value of ja is based on a four-layer, 4 3, 2.5 oz copper board, as per jedec standard. for additional information, see the an-772 application note, a design and manufacturing guide for the lead frame chip scale (lfcsp) . thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 7. thermal resistance package type ja jc unit 20-lead, 0.5 mm pitch lfcsp 38 4.2 c/w esd caution
adp5043 rev. 0 | page 8 of 32 pin configuration and fu nction descriptions notes 1. exposed pad should be connected to agnd. 2. nc = no connect. do not connect to this pin. the pin should be left floating. 14 13 12 1 3 4 nc 15 wstat gnd wdi2 11 vout1 nc vin2 2 vout2 en2 5 nrsto 7 v i n 1 6 a v i n 8 s w 9 p g n d 1 0 e n 1 1 9 w d i 1 2 0 1 8 w m o d 1 7 m o d e 1 6 g n d adp5043 mr top view (not to scale) 09682-002 figure 2. pin configuration table 8. pin function descriptions pin no. mnemonic description 1 nc do not connect to this pin. the pin should be left floating. 2 vout2 ldo output voltage and sensing input. 3 vin2 ldo input supply (1.7 v to 5.5 v). 4 en2 enable ldo. en2 = high: turn on the ldo; en2 = low: turn off the ldo. 5 nrsto open-drain reset output, active low. 6 avin regulators housekeeping and supervisory input supply (2.3 v to 5.5 v). 7 vin1 buck input supply (2.3 v to 5.5 v). 8 sw buck switching node. 9 pgnd dedicated power ground for buck regulator. 10 en1 enable buck. en1 = high: turn on buck; en1 = low: turn off buck. 11 vout1 buck sensing node. 12 wdi2 watchdog 2 (long timeout) refresh input from processo r. this pin can be disabled only by a factory option. 13 gnd connect to the ground plane. 14 nc do not connect to this pin. the pin should be left floating. 15 wstat open-drain watchdog timeout status. wstat = high: watchdog 1 timeout or power-on reset; wstat = low: watchdog 2 timeout. auto cleared after one second. 16 gnd connect to the ground plane. 17 mode buck mode. mode = high: buck regulator operates in fixed pwm mode; mode = low: (auto mode) buck regulator operates in power save mode (psm) at light load and in constant pwm at higher load. 18 wmod watchdog mode. wmod = low: watchdog 1 normal mode ; wmod = high: watchdog 1 cannot be disabled by a three-state condition applied on wdi1. wmod has an in ternal 200 k pull-down resistor connected to agnd. 19 wdi1 watchdog 1 refresh input from processor. if wdi1 is in high-z and wmod is low, watchdog 1 is disabled. 20 mr manual reset input, active low. tp agnd analog ground (tp = exposed thermal pa d). exposed pad should be connected to agnd.
adp5043 rev. 0 | page 9 of 32 typical performance characteristics vin1 = vin2 = avin = 5.0 v, t a = 25c, unless otherwise noted. ch1 2.0v/div 1m ? b w 20.0m ch2 2.0v/div 1m ? b w 20.0m a ch1 1.76v 200s/div 20.0ns/pt 1 2 vout1 vout2 09682-003 3.22 3.24 3.26 3.28 3.30 3.32 3.34 output voltage (v) output current (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 +25c ?40c +85c 09682-007 figure 3. 3-channel start-up waveforms figure 6. buck load regulation across temperature, v out1 = 3.3 v, auto mode 1.775 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 1.825 1.830 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current (a) output voltage (v) +25c ?40c +85c 09682-008 0 0.1 0.2 0.3 0.4 0.5 0.6 1.0 0.9 0.8 0.7 2.32.83.33.84.34.85.3 system quiescent current (ma) input voltage (v) v out1 = 1.5v, v out2 = 3.3v 09682-004 figure 4. system quiescent current (sum of all the input currents) vs. input voltage, v out1 = 1.5 v, v out2 = 3.3 v figure 7. buck load regulation across temperature, v out1 = 1.8 v, auto mode ch1 2.0v/div 1m ? b w 20.0m ch2 2.0v/div 1m ? b w 500m ch3 100ma/div 1m ? b w 20.0m ch4 5.0v/div 1m ? b w 500m a ch1 2.92v 50s/div 50.0ms/s 20.0ns/pt 2 4 1 3 sw vout1 en iin 09682-005 1.784 1.785 1.786 1.787 1.788 1.789 1.790 1.791 1.792 1.793 1.794 1.795 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?40c +25c +85c output current (a) output voltage (v) 09682-009 figure 5. buck startup, v out1 = 1.8 v, i out1 = 20 ma figure 8. buck load regulation across temperature, v out1 = 1.8 v, pwm mode
adp5043 rev. 0 | page 10 of 32 1.790 1.791 1.792 1.793 1.794 1.795 1.796 1.797 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current (a) output voltage (v) v in = 5.5v v in = 4.5v v in = 3.6v 09682-010 figure 9. buck load regulation across input voltage, v out1 = 1.8 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 3.6v 4.5v 5.5v 09682-011 figure 10. buck efficiency vs. load current, across input voltage, v out1 = 3.3 v, auto mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) 3.6v 4.5v 5.5v 09682-012 figure 11. buck efficiency vs. load current, across input voltage, v out1 = 3.3 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) 2.4v 3.6v 4.5v 5.5v 09682-013 figure 12. buck efficiency vs. load current, across input voltage, v out1 = 1.8 v, auto mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) 2.4v 3.6v 4.5v 5.5v 09682-014 figure 13. buck efficiency vs. load current, across input voltage, v out1 = 1.8 v, pwm mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 efficiency (%) output current (a) +25c ?40c +85c 09682-015 figure 14. buck efficiency vs. load current, across temperature, v out1 = 1.8 v, pwm mode
adp5043 rev. 0 | page 11 of 32 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) +25c ?40c +85c 09682-016 figure 15. buck efficiency vs. load current, across temperature, v out1 = 3.3 v, auto mode 0 10 20 30 40 50 60 70 80 90 100 0.0001 0.001 0.01 0.1 1 efficiency (%) output current (a) +25c ?40c +85c 09682-017 figure 16. buck efficiency vs. load current, across temperature, v out1 = 1.8 v, auto mode 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2 . 63 . 64 . 65 . 6 input voltage (v) output current (a) 09682-018 figure 17. buck dc current capability vs. input voltage, v out1 = 1.8 v 2.85 2.90 2.95 3.00 3.05 3.10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 frequency (mhz) +25c ?40c +85c output current (a) 09682-019 figure 18. buck switching frequency vs. output current, across temperature, v out1 = 1.8 v, pwm mode ch1 20.0mv/div b w 20.0m ch2 200ma/div 1m ? b w 20.0m ch3 2.0v/div 1m ? b w 20.0m a ch1 2.4mv 5.0s/div 20.0ms/s 50.0ns/pt 1 2 3 vout i sw sw 09682-020 figure 19. typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto mode ch1 2.0v/div 1m ? b w 20.0m ch2 50.0mv/div b w 20.0m ch3 500ma/div b w 20.0m a ch1 1.56mv 5.0s/div 200ms/s 5.0ns/pt 2 3 1 voutx i sw sw 09682-021 figure 20. typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, auto mode
adp5043 rev. 0 | page 12 of 32 ch1 2.0v/div 1m ? b w 20.0m ch2 50.0mv/div b w 20.0m ch3 500ma/div b w 20.0m a ch1 1.56mv 500ns/div 200ms/s 5.0ns/pt 2 3 1 voutx i sw sw 09682-022 figure 21. typical waveforms, v out1 = 1.8 v, i out1 = 30 ma, pwm mode ch1 20.0mv/div b w 20.0m ch2 200ma/div 1m ? b w 20.0m ch3 2.0v/div 1m ? b w 20.0m a ch1 2.4mv 200ns/div 500ms/s 2.0ns/pt 1 2 3 voutx i sw sw 09682-023 figure 22. typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode ch1 3v/div b w 20.0m ch2 50mv/div b w 20.0m ch3 900mv/div 1m ? b w 20.0m a ch3 4.79v 100s/div 10.0ms/s 100ns/pt 1 3 vinx voutx sw 2 09682-024 figure 23. buck response to line transient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode ch2 50mv/div b w 20.0m ch3 1v/div 1m ? b w 20.0m ch4 2v/div 1m ? b w 20.0m a ch3 4.96mv 100s/div 20ms/s 100ns/pt 2 3 4 vinx voutx sw 09682-025 figure 24. buck response to line transient, v in = 4.5 v to 5.0 v, v out1 = 1.8 v, pwm mode ch1 4v/div b w 20.0m ch2 50mv/div 1m ? b w 20.0m ch3 50ma/div 1m ? b w 20.0m a ch3 44ma 200s/div 10ms/s 100ns/pt 2 3 1 sw voutx iout 09682-026 figure 25. buck response to load transient, i out1 from 1 ma to 50 ma, v out1 = 3.3 v, auto mode ch1 4v/div b w 20.0m ch2 50mv/div b w 20.0m ch3 50ma/div 1m ? b w 20.0m a ch3 28ma 200s/div 5ms/s 200ns/pt 2 3 1 voutx sw v out load 09682-027 figure 26. buck response to load transient, i out2 from 1 ma to 50 ma, v out1 = 1.8 v, auto mode
adp5043 rev. 0 | page 13 of 32 a ch3 86ma 2 3 1 voutx sw load ch1 4v/div b w 20.0m ch2 50mv/div b w 20.0m ch3 50ma/div 1m ? b w 20.0m 200s/div 10ms/s 100ns/pt 09682-028 figure 27. buck response to load transient, i out1 from 20 ma to 140 ma, v out1 = 3.3 v, auto mode 3 4 2 vout1 load sw ch2 4v/div 1m ? b w 20.0m ch3 50mv/div 1m ? b w 20.0m ch4 50ma/div 1m ? b w 20.0m 200s/div 50ms/s 20ns/pt a ch3 145ma 09682-029 figure 28. buck response to load transient, i out1 = 20 ma to 180 ma, v out1 = 1.8 v, pwm mode 1 2 3 voutx i in en a ch2 1.14v ch1 1v/div 1m ? b w 500m ch2 3v/div 1m ? b w 500m ch3 50ma/div 1m ? b w 20.0m 100s/div 1ms/s 1.0s/pt 09682-031 figure 29. ldo startup, v out2 = 3.3 v, i out2 = 5 ma 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.0001 0.001 0.01 0.1 output voltage (v) output current (a) 3.6v 4.5v 5.0v 5.5v 09682-035 figure 30. ldo load regulation across input voltage, v out2 = 3.3 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.0001 0.001 0.01 0.1 output voltage (v) output current (a) +85c +25c ?40c 09682-036 figure 31. ldo load regulation across temperature, v in2 = 3.6 v, v out2 = 3.3 v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 3.325 3 . 54 . 55 . 05 . 5 output voltage (v) input voltage (v) 100a 1ma 10ma 100ma 150ma 09682-037 figure 32. ldo line regula tion across output load, v out2 = 3.3 v
adp5043 rev. 0 | page 14 of 32 0 0 . 0 50 . 1 00 load (a) current (a) . 1 5 0 50 100 150 200 250 09682-038 figure 33. ldo ground current vs. output load, v out2 = 2.8 v 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 ground current (ma) input voltage (v) 1a 100a 1ma 10ma 100ma 150ma 09682-039 figure 34. ldo ground current vs. input voltage, across output load, v out2 = 2.8 v 3 1 vout iout ch1 50mv/div 1m ? b w 500m ch3 50ma/div 1m ? b w 20.0m 200s/div 500ks/s 2.0s/pt a ch3 28ma 09682-040 figure 35. ldo response to load transient, i out2 from 1 ma to 80 ma, v out2 = 3.3 v 2 1 2 2 ch1 10.0mv/div ch2 800mv/div a ch2 5.33v 1m ? b w 20.0m vout vin b w 20.0m 09682-042 figure 36. ldo response to line transient, v in2 = 4.5 v to 5.5 v, v out2 = 3.3 v load current (a) output voltage (v) 0 0.1 0.2 0.3 0.5 0 1.0 1.5 2.0 2.5 3.0 0.4 0.5 0.6 0.7 0.8 5.5v 4.5v 3.6v 09682-056 figure 37. ldo output current capability vs. output voltage load (ma) rms noise (v) 100 10 v out = 3.3v; v in = 5v v out = 3.3v; v in = 3.6v v out = 2.8v; v in = 3.1v v out = 1.5v; v in = 5v v out = 1.5v; v in = 1.8v 0.0001 0.001 0.01 0.1 1 10 100 1k 0 9682-045 figure 38. ldo output noise vs. load current, across input and output voltage
adp5043 rev. 0 | page 15 of 32 ? 10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 1ma 10ma 100ma 200ma 300ma 0 9682-050 v out2 = 3.3v, v in2 = 3.6v, i load = 300ma v out2 = 1.5v, v in2 = 1.8v, i load = 300ma v out2 = 2.8v, v in2 = 3.1v, i load = 300ma noise (v/ hz) 100 10 1 0.1 0.01 1 10 100 1k frequency (hz) 10k 100k 1m 09682-055 figure 39. ldo output noise spectr um, across input and output voltage figure 41. ldo psrr vs. frequency, v in2 = 3.1 v, v out2 = 2.8 v ? 10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 1ma 10ma 100ma 200ma 300ma 0 9682-049 ? 10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 1ma 10ma 100ma 200ma 0 9682-051 figure 40. ldo psrr across output load, v in2 = 3.3 v, v out2 = 2.8 v figure 42. ldo psrr vs. frequency, v in2 = 5 v, v out2 = 3.3 v
adp5043 rev. 0 | page 16 of 32 theory of operation soft start pwm/psm control buck1 driver and antishoot through oscillator v ref thermal shutdown system undervoltage lock out reset generator debounce pwm comp vdda vdda gm error amp psm comp low current i limit adp5043 v out1 wmod enwd1 enwd2 vin1 avin sw pgnd en1 enbk enldo mode mode en2 sel opmode_fuses agnd vin2 ldo control r1 r2 enbk 75? enldo 600 ? c by a vdda r0 r1 mr wdi1 200k ? vdda 52k? 40k ? watchdog status monitor wdi2 poff poff vout2 nrsto wstat enable and mode control watchdog detector1 watchdog detector2 09682-057 figure 43. functional block diagram power management unit the adp5043 is a micro power management unit (micro pmu) combing one step-down (buck) dc-to-dc regulator, one low dropout linear regulator (ldo), and a supervisory circuit, with dual watchdog, for processor control. the regulators are activated by a logic level high applied to the respective en pins. en1 controls the buck regulator while en2 controls the ldo. the adp5043 has factory programmed output voltages and reset voltage threshold. other features available in this device are the mode pin to control the buck switching operation, a status pin (wstat) informing the external processor which watchdog caused a reset, and a push-button reset input (nrsto). when a regulator is turned on, the output voltage is controlled through a soft start circuit, which prevents a large inrush current due to the discharged output capacitors. the buck regulator can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the switching frequency of the buck is always constant and does not change with the load current. if the mode pin is at a logic low level, the switching regulator operates in auto pwm/psm mode. in this mode, the regulator operates at fixed pwm frequency when the load current is above the power saving current threshold. when the load current falls below the power saving current threshold, the regulator enters power saving mode where the switching occurs in bursts. the burst repetition rate is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses.
adp5043 rev. 0 | page 17 of 32 thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off the buck and ldo. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 20c hysteresis is included in the thermal shutdown circuit so that if thermal shutdown occurs, the buck and ldo do not return to normal operation until the on-chip temperature drops below 130c. when coming out of thermal shutdown, a soft start is initiated. undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated in the adp5043. if the input voltage on avin drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channel, both the power switch and the synchronous rectifier turn off. when the voltage on avin rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for 5 v applications. for these models, the device hits the turn-off threshold when the input supply drops to 3.65 v typical. enable/shutdown the adp5043 has individual control pins for each regulator. a logic level high applied to the enx pin activates a regulator; a logic level low turns off a regulator. when regulators are turned off after a watchdog 2 event (see the watchdo g 2 input section), the reactivation of the regulator occurs with a factory programmed order (see table 9 ). the delay between the regulator activation ( t d1 , t d2 ) is 2 ms. table 9. adp5043 regulators sequencing regseq[1:0] regulators sequence (first to last) 0 0 ldo to buck 0 1 buck to ldo 1 0 buck to ldo 1 1 no sequence, all regulators start at same time buck section the buck uses a fixed frequency and high speed current-mode architecture. the buck operates with an input voltage of 2.3 v to 5.5 v. control scheme the buck operates with a fixed frequency current-mode pwm control at medium to high loads for high efficiency; operation shifts to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the integrated switch is adjusted to regulate the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner that produces a higher output voltage ripple. during part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the buck operates at a fixed frequency of 3 mhz, set by an internal oscillator. at the start of each oscillator cycle, the high-side pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the low- side nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. power save mode (psm) the buck smoothly transitions to psm operation when the load current decreases below the psm current threshold. when the buck enters power save mode, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level that is approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle state. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current stays below the psm current threshold. psm current threshold the psm current threshold is set to 100 ma. the buck employs a scheme that enables this current to remain accurately con- trolled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to, and exit from, the psm mode. the psm current threshold is optimized for high efficiency over all load currents. short-circuit protection the buck includes frequency foldback to prevent current runaway with a hard short on the output. when the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter.
adp5043 rev. 0 | page 18 of 32 current limit the buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a dropping input voltage or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. ldo section the adp5043 contains one ldo with a low quiescent current that provides an output current up to 300 ma. the low, 15 a typical, quiescent current at no load makes the ldo ideal for battery-operated portable equipment. the ldo operates with an input voltage range of 1.7 v to 5.5 v. the wide operating range makes this ldo suitable for a cascade configuration where the ldo supply voltage is provided from the buck regulator. the ldo also provides high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with a small 1 f ceramic input and output capacitors. the ldo is optimized to supply analog circuits by offering better noise performance than the buck regulator. internally, an ldo consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is con- trolled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, reducing the current flowing to the output. supervisory section the adp5043 provides microprocessor supply voltage super- vision by controlling the reset input of the microprocessor. code execution errors are avoided during power-up, power- down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. in addition, problems with microprocessor code execution can be monitored and corrected with a dual-watchdog timer. reset output the adp5043 has an active-low, open-drain reset output. this output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 v. the resistor should comply with the logic low and logic high voltage level requirements of the microprocessor while supplying input current and leakage paths on the nrsto pin. a 10 k pull-up resistor is adequate in most situations. the reset output is asserted when the monitored rail is below the reset threshold (v th ), when wdi1 or wdi2 is not serviced within the watchdog timeout period (t wd1 and t wd2 ). reset remains asserted for the duration of the reset active timeout period (t rp ) after the monitored rail rises above the reset threshold or after the watchdog timer times out. figure 44 illustrates the behavior of the reset output, nrsto, and it assumes that vout2 is selected as the rail to be monitored and supplies the external pull- up connected to the nrsto output. rsto nrsto t rd t rd t rp1 t rp1 vout2 v th v th 0v 1v 0v 1v 0v 09682-058 figure 44. reset timing diagram the reset threshold voltage and the sensed rail (vout1, vout2, or avin) are factory programmed. refer to table 15 for a complete list of the reset thresholds available for the adp5043. when monitoring the input supply voltage, avin, if the selected reset threshold is below the uvlo level (factory programmable to 2.25 v or 3.6 v) the reset output, nrsto, is asserted low as soon as the input voltage falls below the uvlo threshold. below the uvlo threshold, the reset output is maintained low down to ~1 v vin. this is to ensure that the reset output is not released when there is sufficient voltage on the rail supplying a processor to restart the processor operations. manual reset input the adp5043 features a manual reset input ( mr ) which, when driven low, asserts the reset output. when mr transitions from low-to-high, reset remains asserted for the duration of the reset active timeout period before deasserting. the mr input has a 52 k, internal pull-up, connected to avin, so that the input is always high when unconnected. an external push-button switch can be connected between mr and ground so that the user can generate a reset. debounce circuitry for this purpose is integrated on chip. noise immunity is provided on the mr input, and fast, negative-going transients of up to 100 ns (typical) are ignored. a 0.1 f capacitor between mr and ground provides additional noise immunity.
adp5043 rev. 0 | page 19 of 32 watchdog 1 input watchdog 2 input the adp5043 features a watchdog timer that monitors microprocessor activity. the watchdog timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (wdi1), which detects pulses as short as 80 ns. if the timer counts through the preset watchdog timeout period (t wd1 ), an output reset is asserted. the microprocessor is required to toggle the wdi1 pin to avoid being reset. failure of the microprocessor to toggle wdi1 within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor into a known state. the adp5043 features an additional watchdog timer that monitors microprocessor activity in parallel with the first watchdog but with a much longer timeout. this provides additional security and safety in case watchdog 1 is incorrectly strobed. a timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (wdi2), which detects pulses as short as 8 s. if the timer counts through the preset watchdog timeout period (t wd2 ), reset is asserted, followed by a power cycle of all regulators. the microprocessor is required to toggle the wdi2 pin to avoid being reset and powered down. failure of the microprocessor to toggle wdi2 within the timeout period, therefore, indicates a code execution error, and the reset output nrsto is forced low for t rp2 . then, all the regulators are turned off for the t poff time. after the t poff period, the regulators are reactivated according to a predefined sequence (see table 9 ). finally, the reset line (nrsto) is asserted for t rp1 . this guaran- tees a clean power-up of the system and proper reset. as well as logic transitions on wdi1, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the monitored rail. when reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. watchdog 1 timer can be disabled by leaving wdi1 floating or by three-stating the wdi1 driver. the pin wmod controls the watchdog 1 operating mode. if wmod is set to logic level low, watchdog 1 is enabled as long as wdi1 is not in three-state. if wmod is set to logic level high, watchdog 1 is always active and cannot be disabled by a three-state condition. wmod input has an internal 200 k pull-down resistor. as well as logic transitions on wdi2, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the v th monitored rail which can be factory programmable between vout1, vout2, and avin (see table 20 ). when reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. watchdog 1 timeout is factory set to two possible values, as indicated in table 17 . watchdog 2 timeout is factory set to seven possible values as indicated in table 18 . one additional option allows watchdog 2 to be factory disabled. wdi1 nrsto t rp1 t rp1 t wd1 v sensed v th 1v 0v 0v 0v 09682-059 figure 45. watchdog 1 timing diagram a vin/vinx/enx vout1 vout2 nrsto wdi2 wstat v th 0v 0v 0v 0v t poff t d1 t d2 t d1 t rp1 t rp2 t rp1 t wdclear t d2 t wd2 09682-060 figure 46. watchdog 2 timing diagram (assu ming that vout2 is the monitored rail)
adp5043 rev. 0 | page 20 of 32 watchdog status indicator in addition to the dual watchdog function, the adp5043 features a watchdog status monitor available on the wstat pin. this pin can be queried by the external processor to determine the origin of a reset. wstat is an open-drain output. wstat outputs a logic level depending on the condition that has generated a reset. wstat is forced low if the reset was generated because of a watchdog 2 timeout. wstat is pulled high, through external pull-up, for any other reset cause (watchdog 1 timeout, power failure or monitored voltage be low threshold). the status monitor is automatically cleared (set to logic level high) 10 seconds after the nrsto low-to-high transition (t wdclear ). the processor firmware must be designed to read the wstat flag before t wdclear expiration after a watchdo g 2 res et. the wstat flag is not updated in the event of a reset due to a low voltage threshold detection or watchdog 1 event occurring within 10 seconds after an nrsto low-to-high transition. in this situation, wstat maintains the previous state (see the state flow in figure 47 ). the external processor can further distinguish a reset caused by a watchdog 1 timeout from a power failure, status monitor wstat indicating a high level, by implementing a ram check or signature verification after reset. a ram check or signature failure indicates that a power failure has occurred, whereas a ram check or signature validation indicates that a watchdog 1 timeout has occurred. table 10 shows the possible watchdog decoded statuses. table 10. watchdog status decoding wstat ram checksum reset origin high failed power failure high ok watchdog 1 low don't care watchdog 2 n op o wer a pplied to a vi n . all regulators and supervisory turned off no power por standby wstat = high wstat = high reset normal wstat = low avin < vuvlo all enx = low avin > vuvlo transition state transition state transition state end of por wstat timeout (t wdclear ) wstat = 1 transition state all regulators and supervisor activated wdog2 timeout (t wd2 ) wstat = 0 end of (t poff ) pulse wdog1 timeout (t wd1 ) and wstat timeout wstat = 1 wdog1 timeout (t wd1 ) all enx = high active power off reset short avin < vuvlo end of reset pulse (t rp2 ) internal circuit biased regulators and supervisory not activated avin < vuvlo a vin < vuvlo vmon < vth end of reset pulse (t rp1 ) 09682-061 figure 47. adp5043 state flow
adp5043 rev. 0 | page 21 of 32 applications information buck external component selection trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in figure 48 . adp5043 microprocessor v cc vout1 vout2 nrsto wdi1 reset wdi2 vin1 i/o i/o vcore vddio 09682-067 figure 48. typical applications circuit inductor the high switching frequency of the buck regulator of the adp5043 allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. suggested inductors are shown in table 1 1 . the peak-to-peak inductor current ripple is calculated using the following equation: lfv vvv i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 )( ripple max load peak i ii + = table 11. suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 1.6 0.8 0.8 150 26 taiyo yuden cbmf1608t1r0m 1.6 0.8 0.8 290 90 coilcraft epl2014-102ml 2.0 2.0 1.4 900 59 tdk glfr1608t1r0m-lr 1.6 0.8 0.8 230 80 coilcraft 0603ls-102 1.8 1.69 1.1 400 81 toko mdt2520-cn 2.5 2.0 1.2 1350 85 inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the buck is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low emi. output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing the capacitor value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec- trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tem- perature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are highly recommended for best performance. y5v and z5u dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu- lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 9.2481 f at 1.8 v, as shown in figure 49 . substituting these values in the equation yields c eff = 9.2481 f (1 ? 0.15) (1 ? 0.1) = 7.0747 f to guarantee the performance of the buck regulator, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0123456 dc bias voltage (v) capacitance (f) 09682-062 figure 49. typical capacitor performance
adp5043 rev. 0 | page 22 of 32 the peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: () out sw ripple out sw in ripple cf i clf v v = = 8 2 2 capacitors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: rippl e ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. table 12. suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 the buck regulator requires 10 f output capacitors to guaran- tee stability and response to rapid load variations and to transition in and out the pwm/psm modes. in certain applications, where the buck regulator powers a processor, the operating state is known because it is controlled by software. in this condition, the processor can drive the mode pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load variation when working in psm mode (see figure 50 ). sw vin1 vin2 vout1 vout2 nrsto pgnd l1 1h c6 4.7f c4 1f r1 100k? c2 4.7f c3 1f avin r filt 30? micro pmu adp5043 processor vcore vddio reset gpio1 mode wdix gpio2 enx gpio[x:y] 2 v in 2.3v to 5.5v 09682-063 figure 50. processor system power management with psm/pwm control input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v vvv ii ) ( )( ? to minimize supply noise, place the input capacitor as close to the vin pin of the buck as possible. as with the output capacitor, a low esr input capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 f and a maximum of 10 f. suggested capacitors are shown in tabl e 13 . table 13. suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me19d 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 panasonic x5r ecj-0eb0j475m 0402 6.3 ldo capacitor selection output capacitor the adp5043 ldo is designed for operation with small, space- saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the esr value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 or less is recommended to ensure stability of the ldo. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ldo to large changes in load current. input bypass capacitor connecting a 1 f capacitor from vin2 to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. table 10. suggested 1.0 f capacitors vendor type model case size voltage rating (v) murata x5r grm155r61a105me15 0402 10.0 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv-f 0402 10.0
adp5043 rev. 0 | page 23 of 32 input and output capacitor properties use any good quality ceramic capacitors with the adp5043 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors mu st have a dielectric adequate to ensure the minimum capacitance over the necessary tempe- rature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are highly recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera- ture range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0123456 dc bias voltage (v) capacitance (f) 09682-064 figure 51. capacitance vs. voltage characteristic use the following equation to determine the worst-case capa- citance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v as shown in figure 51 . substituting these values into the following equation yields: c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp5043, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. supervisory section watchdog 1 in put current to minimize watchdog input current (and minimize overall power consumption), leave wdi1 low for the majority of the watchdog timeout period. when driven high, wdi1 can draw as much as 25 a. pulsing wdi1 low-to-high-to-low at a low duty cycle reduces the effect of the large input current. when wdi1 is unconnected and wmod is set to logic level low, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out. negative-going v cc transients to avoid unnecessary resets caused by fast power supply transients, the adp5043 is equipped with glitch rejection circuitry. the typical performance characteristic in figure 52 plots the monitored rail voltage, v th , transient duration vs. the transient magnitude. the curve shows combinations of transient magnitude and duration for which a reset is not generated for a 2.93 v reset threshold part. for example, with the 2.93 v threshold, a transient that goes 100 mv below the threshold and lasts 8 s typically does not cause a reset, but if the transient is any larger in magnitude or duration, a reset is generated. 1000 900 800 700 600 500 400 300 200 100 0 0.1 1 10 100 comparator overdrive (% of v th ) transient duration (s) 09682-065 figure 52. maximum v th transient duration vs. reset threshold overdrive
adp5043 rev. 0 | page 24 of 32 watchdog software considerations in implementing the watchdog strobe code of the microprocessor, quickly switching wdi1 low-to-high and then high-to-low (minimizing wdi1 high time) is desirable for current consumption reasons. however, a more effective way of using the watchdog function can be considered. a low-to-high-to-low wdi1 pulse within a given subroutine prevents the watchdog from timing out. however, if the sub- routine becomes stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle wdi1. a more effective coding scheme for detecting this error involves using a slightly longer watchdog timeout. in the program that calls the subroutine, wdi1 is set high. the subroutine sets wdi1 low when it is called. if the program executes without error, wdi1 is toggled high and low with every loop of the program. if the subroutine enters an infinite loop, wdi1 is kept low, the watchdog times out, and the microprocessor is reset (see figure 53 ). start set wdi high program code subroutine set wdi low return infinite loop: watchdog times out reset 09682-066 figure 53. watchdog flow diagram the second watchdog, refreshed through the wdi2 pin, is useful in applications where safety is a very critical factor and the system must recover from unexpected operations, for example, a processor stuck in a continuous loop where watchdog 1 is kept refreshed or environmental conditions that may unset or damage the processor port controlling the wdi1 pin. in the event of a watchdog 2 timeout, the adp5043 power cycles all the supplied rails to guarantee a clean processor start. pcb layout guidelines p oor layout can affect the adp5043 performance, causing electro-magnetic interference (emi) and electromagnetic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following guidelines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
adp5043 rev. 0 | page 25 of 32 power dissipation/thermal considerations the adp5043 is a highly efficient micro pmu, and in most cases the power dissipated in the device is not a concern. however, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125c). when the junction temperature exceeds 150c, the adp5043 turns off all the regulators, allowing the device to cool down. once the die temperature falls below 135c, the adp5043 resumes normal operation. this section provides guidelines to calculate the power dissi- pated in the device and to make sure the adp5043 operates below the maximum allowable junction temperature. the efficiency for each regulator on the adp5043 is given by 100% = in out p p (1) where: is efficiency. p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1- )/ (2b) the power dissipation of the supervisory function is small and can be neglected. power dissipation can be calculated in several ways. the most intuitive and practical is to measure the power dissipated at the input and all the outputs. the measurements should be performed at the worst-case conditions (voltages, currents, and temperature). the difference between input and output power is dissipated in the device and the inductor. use equation 4 to derive the power lost in the inductor, and from this use equation 3 to calculate the power dissipation in the adp5043 buck regulator. a second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, while the power lost on the ldo is calculated using equation 12. once the buck efficiency is known, use equation 2b to derive the total power lost in the buck regulator and inductor, use equation 4 to derive the power lost in the inductor, and thus calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the ldo to find the total dissipated power. it should be noted that the buck efficiency curves are typical values and may not be provided for all possible combinations of v in , v out , and i out . to account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. a third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by equation 8 to equation 11 and the losses in the ldo provided by equation 12. buck regulator power dissipation the power loss of the buck regulator is approximated by p loss = p dbuck + p l (3) where: p dbuck is the power dissipation on the adp5043 buck regulator. p l is the inductor power losses. the inductor losses are external to the device and they dont have any effect on the die temperature. the inductor losses are estimated (without core losses) by l rmsout1 l dcr ip ? 2 )( (4) where i out1(rms) is the rms load current of the buck regulator. /12+1 )( r i i out1 rmsout1 = (5) where r is the inductor ripple current. r v out1 (1- d )/( i out1 l f sw ) (6) d = v out1 / v in1 (7) f sw is switching frequency. l is inductance. dcr l is the inductor series resistance. d is duty cycle. the adp5043 buck regulator power dissipation, p dbuck , includes the power switch conductive losses, the switch losses, and the transition losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application will be. equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran (8) the power switch conductive losses are due to the output current, i out1 , flowing through the pmosfet and the nmosfet power switches that have internal resistance, r dson-p and r dson-n . the amount of conductive power loss is found by: p cond = [ r dson-p d + r dson-n (1 ? d)] i out1 2 (9) for the adp5043, at 125c junction temperature and vin = 3.6 v, r dson-p is approximately 0.2 , and r dson-n is approximately 0.16 . at vin = 2.3 v, these values change to 0.31 and 0.21 respectively, and at vin = 5.5 v, the values are 0.16 and 0.14 .
adp5043 rev. 0 | page 26 of 32 switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by: p sw = ( c gate-p + c gate-n ) v in1 2 f sw (10) where: c gate-p is the pmosfet gate capacitance. c gate-n is the nmosfet gate capacitance. for the adp5043, the total of ( c gate-p + c gate-n ) is ~150 pf. the transition losses occur because the pmosfet cannot be turned on or off instantaneously, and the sw node takes some time to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by: p tran = v in1 i out1 ( t rise + t fall ) f sw (11) where t rise and t fall are the rise time and the fall time of the switching node, sw. for the adp5043, the rise and fall times of sw are in the order of 5 ns. if the equations and parameters previously given are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter performance also depends on the choice of passive components and board layout, so a sufficient safety margin should be included in the estimate. ldo regulator power dissipation the power loss of a ldo regulator is given by: p dldo = [( v in ? v out ) i load ] + ( v in i gnd ) (12) where: i load is the load current of the ldo regulator. v in and v out are input and output voltages of the ldo, respectively. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is small and it can be ignored. junction temperature the total power dissipation in the adp5043 simplifies to: p d = {[ p dbuck + p dldo1 + p dldo2 ]} (13) in cases where the board temperature (t a ) is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula: t j = t a + ( p d ja ) (14) the typical ja value for the 20-lead, 4 mm 4 mm lfcsp is 38c/w, see table 7 . a very important factor to consider is that ja is based on a four-layer 4 3, 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers. it is important to maximize the copper used to remove the heat from the device, and copper exposed to air dissipates heat better than copper used in the inner layers. the thermal pad (tp) should be connected to the ground plane with several vias as shown in figure 55 . if the case temperature can be measured, the junction temperature is calculated by: t j = t c + ( p d jc ) (15) where: t c is the case temperature. jc is the junction-to-case thermal resistance provided in table 7 . when designing an application for a particular ambient temperature range, calculate the expected adp5043 power dissipation (p d ) due to the losses of all channels by using equation 8 to equation 13. from this power calculation, the junction temperature, t j , can be estimated using equation 14. the reliable operation of the buck regulator and the ldo regulator can be achieved only if the estimated die junction temperature of the adp5043 (equation 14) is less than 125c. reliability and mean time between failures (mtbf) is highly affected by increasing the junction temperature. additional information about product reliability can be found in the analog devices, inc., reliability handbook .
adp5043 rev. 0 | page 27 of 32 evaluation board schematics and artwork 09682-068 sw vout1 pgnd mode c6 10f l1 1h vin1 tp1 tp2 tp6 tp5 nc en1 vin2 en2 c2 1f vout2 tp12 nc c5 4.7f vin1 = 2.3v to 5.5v a vin r filt 30? vin2 = 1.7v to 5.5v c1 1f tp4 tp11 wstat wmod wdi1 wdi2 nrsto tp9 tp10 tp7 tp3 tp8 en_bk buck en_ldo ldo supervisor avin avin gnd gnd agnd mr v out1 @ 800ma v out2 @ 300ma figure 54. evaluation board schematic suggested layout 0 .5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2 .5 3 3 .5 mm c3 - 1uf 3v/xr5 0402 6. l1?1uh 0603 c4 - 1uf 10v/xr 5 0402 mm 5.5 6 6.5 n.c. vout 2 vin 2 en2 avin vin 1 sw pgnd mr wdi 1 w mod mode wstat n.c. gn d wdi 2 agnd nrsto en1 vout 1 gn d 4 4 .5 5 5 .5 6 c6 - 10uf 6.3v/xr5 0603 c5 - 4.7uf 10v/xr5 0603 3.3v wd i 1 mod 1.5v mr - 1 u v / xr 4 02 en 2 rst o ou t 1 st at 7 top layer 2nd layer en adp5043 mod e r 10 ohms 0402 g g vias legend: ppl = power plane (+4v) gpl = ground plane 09682-069 figure 55. layout
adp5043 rev. 0 | page 28 of 32 bill of materials table 14. reference value part number vendor package c1, c2 1 f, x5r, 6.3 v lmk105bj105mv-f taiyo yuden 0402 c5 4.7 f, x5r, 10 v lmk107bj475ma-t taiyo yuden 0603 c6 10 f, x5r, 6.3 v jmk107bj106ma-t taiyo yuden 0603 r filt 30 0201/0402 l1 1 h, 0.09 , 290 ma brc1608t1r0m taiyo yuden 0603 1 h, 0.08 , 230 ma glfr1608t1r0m-lr tdk 0603 ic1 dual regulator micro pmu adp5043 analog devices 20-lead lfcsp application diagram 09682-070 fpwm pwm/psm on off r1 r2 poff sw vout1 pgnd mode c6 10f l1 1h vin1 en1 vin2 en2 c2 1f vout2 wstat wdi2 wdi1 nrsto c5 4.7f v in1 = 2.3v to 5.5v v in2 = 1.7v to 5.5v c1 1f v out1 @ 800ma v out2 @ 300ma en_bk buck en_ldo ldo supervisor on off on off 20 4 3 10 7 avin wmod 18 19 12 5 15 2 17 9 11 8 wdog2 wdog1 reset nc 1 nc 14 v dd v dd push-button reset mr main microcontroller tp agnd 13 gnd 16 gnd avin r filt 30? avin 6 ic1 figure 56. application diagram
adp5043 rev. 0 | page 29 of 32 factory programmable options table 15. reset voltage threshold options 1 t a = +25c t a = ?40c to +85c selection min typ max min max unit 111 (for v in = 5 v ? 6%) 4.630 4.700 v 110 (for v out = 3.3 v) 3.034 3.080 3.126 3.003 3.157 v 101 (for v out = 3.3 v) 2.886 2.930 2.974 2.857 3.000 v 100 (for v out = 2.8 v) 2.591 2.630 2.669 2.564 2.696 v 011 (for v out = 2.8 v) 2.463 2.500 2.538 2.438 2.563 v 010 (for v out = 2.5 v ? 6%) 2.350 2.385 v 001 (for v out = 2.2 v ? 6%) 2.068 2.099 v 000 (for v out = 1.8 v ? 6%) 1.692 1.717 v 1 when monitoring avin, the reset threshold selected, by fuse opti on or by the external resistor divided, must be higher than th e uvlo threshold (2.25 v or 3.6 v). table 16. reset timeout options selection min typ max unit 0 24 30 36 ms 1 160 200 240 ms table 17. watchdog 1 timer options selection min typ max unit 0 81.6 102 122.4 ms 1 1.12 1.6 1.92 sec table 18. watchdog 2 timer options selection min typ max unit 000 6 7.5 9 sec 001 watchdog 2 disabled 010 3.2 4 4.8 min 011 6.4 8 9.6 min 100 12.8 16 19.2 min 101 25.6 32 38.4 min 110 51.2 64 76.8 min 111 102.4 128 153.6 min table 19. power-off timing options selection min typ max unit 0 140 200 280 ms 1 280 400 560 ms table 20. reset sensing options selection monitored rail 00 vout1 pin 01 reserved 10 vout2 pin 11 avin 1 pin 1 when monitoring avin, the reset threshold selected, by fuse opti on or by the external resistor divided, must be higher than th e uvlo threshold (2.25 v or 3.6 v). table 21. buck and ldo output voltage options selection output voltage buck 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.3 v, 2.0 v, 1.82 v, 1.8 v, 1.6 v, 1.5 v, 1.4 v, 1.3 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v ldo 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.25 v, 2.0 v, 1.8 v, 1.7 v, 1.6 v, 1.5 v, 1.2 v, 1.1 v, 1 v, 0.9 v, 0.8 v
adp5043 rev. 0 | page 30 of 32 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 57. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-8) dimensions shown in millimeters ordering guide model 1 , 2 regulator settings supervisory se ttings temperature range package description package option ADP5043ACPZ-1-R7 v out1 = 1.5 v wd1 t out = 1.6 sec t j = ?40c to +125c 20-lead lead frame scale package [lfcsp_wq] cp-20-8 v out2 = 3.3 v wd2 t out = 128 min uvlo = 2.25 v reset t out = 200 ms sequencing: ldo, buck poff = 200 ms v th sensing = vout2, 2.93 v adp5043cp-1-evalz evaluation board 1 z = rohs compliant part. 2 monitoring ambient temperature does not guarantee that the junction temperature (t j ) is within the specified temperature l imits. see the power dissipation/thermal considerations section for more information.
adp5043 rev. 0 | page 31 of 32 notes
adp5043 rev. 0 | page 32 of 32 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09682-0-4/11(0)

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